The present invention relates to a clock signal generation circuit of a phase locked loop (PLL) type, and more especially to a clock signal generation circuit applicable to be used in a semiconductor integrated circuit device capable of operating at a high speed with a high frequency.
Recently, there have been developed various semiconductor devices assuming a part as a microprocessor and a peripheral circuit of the microprocessor. Such semiconductor devices are required to be operated with a high frequency, and it is necessary for each semiconductor device to operate in synchronous with clocks in a system and clocks supplied from the outside because a plurality of chips are combined to use. In such a large scale integrated (LSI) circuit which is formed in the semiconductor device operating at a high speed, the clock signal generation circuit using a phase locked loop (PLL) circuit controls an internal clock signal in an LSI in order to decrease a delay of a clock signal of the internal circuit against an input clock signal supplied from the outside to the chip, and in order to make synchronous with clock signals of other LSIs.
FIG. 1 shows a clock signal generation circuit of the PLL type in the conventional semiconductor circuit device. In this example, the clock signal generation circuit comprises a phase locked loop (PLL) circuit 17 and a selector 15.
The PLL circuit 17 comprises a phase comparator 12 for detecting a phase difference between a reference clock signal 10 supplied from the outside and an internal clock signal 16 used in an internal LSI circuit, a loop filter 13 for outputting a direct current corresponding to a phase difference output of the phase comparator 12, and a voltage control oscillator (VCO) 14 of a variable frequency for oscillating at a frequency corresponding to an output voltage of the loop filter 13. The voltage control oscillator 14 supplies a clock signal 16 into the LSI through the selector 15 at normal operation. The internal clock signal 16 is inputted through the LSI circuit into the phase comparator 12 to compare with the reference clock signal 10 supplied from the outside.
In the above construction, when the phases are discrepant between the reference clock signal 10 and the internal clock signal 16, the phase comparator 12 detects the phase difference, and an output potential of the loop filter 13 increases and decreases corresponding to the phase difference. The output signal causes the voltage control oscillator 14 to change an oscillation frequency in the direction to cancel the phase difference. Such operation is repeated in the phase locked loop to decrease the phase difference between two clock signals. When the phase comparator 12 does not detect the phase difference, the loop filter 13 holds an output potential at that time, and the voltage control oscillator 14 continues to generate the internal clock signal 16 whose phase synchronizes with that of the reference clock signal 100 thereby resulting in the PLL circuit 17 being in the locked condition against the reference clock signal. The selector 15 corresponds to a clock selection signal externally supplied to select any of the external clock signal 10 and an internal clock signal outputted from the PLL circuit 17 so as to supply a selected signal to the internal circuit of the semiconductor device. Therefore, it is possible to change over the external clock signal 10 and the internal clock signal 16 to use a switched signal in the internal circuit.
In this manner, by using the PLL circuit 17, the internal clock signal 16 in the LSI perfectly synchronizes without the phase difference against the external reference clock signal 10, thereby resulting in an advantage in which a delay does not occur in the internal clock signal because of a buffering of the input portion.
By the way, the PLL circuit 17 has a limit of a frequency range of the clock signal capable of synchronizing because a change amount (gain) of the oscillating frequency against an input voltage of the voltage control oscillator 14 is set to be optimum within a high frequency level in ordinary operation, for example, in 10-100 MHz. When an input frequency is low enough to correspond to a design frequency, for example, on or under 1 MHz, the gain is too large to largely change the oscillating frequency by a fine change of an input potential influenced by noises, thereby resulting in unstable operation of the PLL circuit. Furthermore, since the voltage control oscillator 14 can not oscillate a clock signal having such a low frequency, the necessary clock signal can not be generated.
Therefore, when a burn-in test for estimating the LSI must be performed at a low clock frequency (low speed) because of no high speed testing device, the PLL circuit 17 can not be locked to generate a synchronous clock signal.
Accordingly, at testing in low speed operation, the selector circuit 15 divides the output clock signal of the PLL circuit 17 and the clock signal in the LSI by the above-mentioned clock selection signal, and directly receives the input clock signal 10 externally supplied as the internal clock signal. Since operation is performed in low speed at this time, the delay of the input clock signal 10 and internal clock signal does not influence operation of the LSI, and it is unnecessary for the PLL circuit 17 to generate the clock signal and it is no problem in operation of the LSI.
However, since the clock signal generation circuit does not operate the PLL circuit 17 at an estimation, the phase locked loop circuit itself is not an object of the estimation. Therefore, since the PLL circuit 17 does not operate in the burn-in testing and an operational stress can not add to only the portion, the entire LSI can not be sufficiently estimated.
Furthermore, since the clock selection signal 11 is supplied from the outside for changing over a clock signal generation source, it is a problem that input terminals for testing (IC package terminals) increase.
Accordingly, even though testing of operation at a low frequency is not performed frequently, it is necessary to set a special mode for the testing and to provide a signal pin for setting the special mode. However, in a static random access memory (SRAM), since the signal pins are limited to provide the signal pins around the side wall of the package, there is a large demerit to providing the specific pin for low speed operation testing.